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In Xilinx FPGAs, a LUT can be used as a serial shift register with one bit input and one bit output using one LUT as SRL32 providing efficient design (instead of cascading up to 32 flip-flops) provided the code. Vivado vhdl 2008. Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching. This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Re: Counter implementation in vhdl. As you noted in your original message, the implementation of your two pieces of code is the same. There is no implementation difference between assigning inside a process but outside any if statement or assigning as a continuous statement. There may be a difference in simulation. VHDL Program Counter, multiple constant driver error-1 VHDL: Internal signal in component not triggered 0 Cannot create latch and counter 0. How to implement a VHDL testbench for verilog module? If this is your first visit, be sure to check out the FAQ by clicking the link above.